Cellular 5G /4G Physical Layer Firmware Engineer
Apple · Hardware
Apply ↗Skills
["C++""Go""Python"]Technology stack
{"programming_languages": ["Python""Go""C++"]"frameworks": []"databases": []"cloud": []"infrastructure": []"data_tools": []"ai_ml": []"other_tools": []}Description
- Implement key 3GPP protocols and control/data path processing algorithms with very tight time, latency and energy budgets by interfacing to specialized cellular ASIC hardware. - Examples of processing include 3GPP channels and procedures such as PDCCH, PDSCH, PBCH, PUCCH, PUSCH, PRACH, UL/DL HARQ, Tracking loops. - Examples of 3GPP algorithmic areas include: - Channel Estimation - Channel State Feedback - Interference Cancellation - Cell Search and Measurement - Beam Measurement - Work with systems engineers to refine signal processing algorithms for efficient firmware/hardware execution - Work with silicon designers to define HW interfaces, processors, bus, DMA, accelerator, and memory subsystems. - Specify, design, and implement the firmware architecture of an innovative mobile wireless communications system. - Assist in the development of pre-silicon emulation systems/virtual platforms and use them for pre-silicon FW design and HW verification. - Evaluate and implement pioneering tools for build, formal verification and test. - Define methodologies and best practices.
Requirements
["Experience with hardware control for physical layer4G/5G data path processing", "Understanding of 5G and 4G 3GPP protocols", "Experience implementing digital signal processing algorithms using special purpose digital signal processing HW.", "Strong understanding of linear algebra and digital signal processing principles.", "Deep understanding of software engineering principles, and core computer science fundamentals.", "Fundamental facility with C and C++, compilers, build and source code control tools.", "Significant experience with memory constrained Real Time Operating Systems (RTOS) and concurrent programming.", "Solid understanding of computer architecture with particular emphasis on the HW/SW interfaces of high speed communication subsystems.", "Experience with silicon prototyping, emulation systems, and virtual platforms.", "Proficiency debugging embedded software systems. Familiarity with UARTs, JTAG, and oscilloscopes.", "Some mainstream OS application level development and Python or Perl scripting experience.", "Preferred: PhD/Master's/Bachelor’s degree in electrical engineering, electronics and telecommunications, computer engineering or computer science is required."]
Roles & responsibilities
["- Implement key 3GPP protocols and control/data path processing algorithms with very tight time, latency and energy budgets by interfacing to specialized cellular ASIC hardware.", "- Examples of processing include 3GPP channels and procedures such as PDCCH, PDSCH, PBCH, PUCCH, PUSCH, PRACH, UL/DL HARQ, Tracking loops.", "- Examples of 3GPP algorithmic areas include:", "- Channel Estimation", "- Channel State Feedback", "- Interference Cancellation", "- Cell Search and Measurement", "- Beam Measurement", "- Work with systems engineers to refine signal processing algorithms for efficient firmware/hardware execution", "- Work with silicon designers to define HW interfaces, processors, bus, DMA, accelerator, and memory subsystems.", "- Specify, design, and implement the firmware architecture of an innovative mobile wireless communications system.", "- Assist in the development of pre-silicon emulation systems/virtual platforms and use them for pre-silicon FW design and HW verification.", "- Evaluate and implement pioneering tools for build, formal verification and test.", "- Define methodologies and best practices."]
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